DFT ATPG Design and Test Engineer

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At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

THE PERSON:

KEY RESPONSIBILITIES:

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the continued evolution of CPU cache array and DFT design practices.

PREFERRED EXPERIENCE:

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
• Strong working knowledge of industry-standard ATPG tools and their application to pattern generation, fault coverage, and product quality.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
• Experience with multi-clock and multi-power-domain designs.
• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
• Experience adapting standard DFT tools or methods to meet the performance requirements of complex, high-frequency designs.
• CPU or cache architecture experience is preferred; strong DFT candidates from related ASIC environments may also be considered.
• Demonstrated success collaborating across design, physical design, product engineering, and geographically distributed teams.
• Interest in continuous improvement and in developing broader expertise across CPU, cache, and silicon design disciplines.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is preferred.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.