ASIC RTL Design Engineer, Interconnect & Memory Systems

The Tesla AI Hardware team is looking for an ASIC RTL Design Engineer specializing in interconnect and memory systems to drive the development of next-generation AI accelerators. In this role, you will focus on the critical data path elements of custom ASICs, including Network on Chip (NoC) architectures, DMA engines, memory controllers, Memory Management Units (MMUs), arbiters, and AXI protocol implementations. You will collaborate closely with system architects, verification engineers, physical design teams, and software/firmware developers to deliver high-performance, power-efficient designs that enable massive-scale AI training and inference. This position is based in Palo Alto, CA, or Austin, TX and offers the opportunity to work oncutting-edgehardware that powers Tesla's autonomous driving and AI initiatives.

• Architect, design, and implement RTL (Verilog/SystemVerilog) for high-performance interconnect and memory subsystems, including NoC topologies, DMA controllers, and AXI-based data pathsoptimizedfor AI workloads
• Develop and document microarchitecture specifications for memory controllers, MMUs, and arbiters to ensure low-latency, high-bandwidth data movement across SoC components
• Define system-level functional requirements for SoC data paths, focusing on throughput, scalability, and integration withcomputeaccelerators
• Perform design analysis, including timing closure, power optimization, and area efficiency, for high-performance memory and interconnect blocks
• Collaborate with cross-functional teams to integrateinterconnectIP into full-chip designs, debug issues, and support silicon bring-up and validation
• Contribute to performance modeling and simulation of data path elements to meet aggressive AI hardware metrics
• Stay abreast of industry trends in high-performance ASIC design and propose innovations for interconnect and memory efficiency

• Degree in Electrical Engineering, Computer Science, or equivalentexperience
• 3+ years of hands-on RTL design experience in SoC interconnect, memory systems, or data path components for custom ASICs
• Strongproficiencyin Verilog orSystemVerilogfor complex digital design
• Solid understanding of AXI protocol and high-performance design techniques (e.g., pipelining, clock domain crossing)
• Experience with synthesis, timing analysis, and linting tools (e.g., Synopsys Design Compiler,SpyGlass)
• Ability to work in a fast-paced, collaborative environment with strong problem-solving skills
• Proventrack recordin Network on Chip (NoC) design, including topology selection, routing algorithms, and QoS mechanisms
• Deepexpertisein DMA engine design, memory controller architectures (e.g., DDR/LPDDR interfaces), MMUs, and priority arbiters for multi-master systems
• Experience with high-performance SoC data path optimization for AI/ML accelerators or HPC applications
• Familiarity with verification methodologies (e.g., UVM) and scripting (Python/Perl) for automation