Director of Physical Design
 Microsoft | |
 United States, California, Mountain View | |
 Sep 26, 2025 | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Director of Physical Design to join the team.
ResponsibilitiesLead a team in defining implementation and execution plan for a schip/SOC, execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc) and drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs). This will involve optimizing technology, libraries, physical design, RTL design, and architecture. Leading the team in defining the implementation and execution plan for a subchip/SOC. Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan. Executing the defined plan to ensure successful tapeout of the subchip/SOC. Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips. Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets. Ensuring that the physical design aspects align with the overall project goals and timelines. Providing technical guidance and mentorship to team members. Overseeing the development and implementation of physical design flows and methodologies. Collaborating with cross-functional teams to address any design challenges and optimize the design for manufacturability. Monitoring progress, identifying risks, and implementing mitigation strategies to ensure project success. Keeping abreast of the latest industry trends, tools, and techniques in physical design to drive innovation and efficiency within the team. You are expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team. Occasional travel may berequired. | |