- Control subsystem development in large mixed-signal ASICs
- Work with system architect to define micro-architecture and RTL development
- Design size/timing/power optimization via micro-architecture/RTL/Synthesis
- Masters degree desired, Bachelor's degree in CS/EE is required.
- 1+ years of relevant experience in ASIC design field.
- Solid ASIC/FPGA design (micro-architecture/implementation) and debugging skills
- Experience in Verilog / SystemVerilog design
- Strong problem-solving skills
- Good verbal/written communication skills and teamwork
- Good knowledge of ASIC design flow/tools, with backend knowledge being a great asset
- Working knowledge of scripting languages like PYTHON and PERL, and C/C++/Assembly programming
- Familiarity with embedded processor & bus functional protocols would be bonus
- Familiarity with Encryption, Ethernet DSP and/or FEC would be a bonus
- Familiarity with external memory interface protocols would be a bonus
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